Field Effect Transistors (FET's) are known in the art. Insulated Gate FET's, more commonly called MOSFET's, are also known in the art. Methods of fabricating n Channel and p Channel MOSFETs are known in the art. The simplest MOSFET model is a switch wherein, if the correct voltage is applied to the MOSFET's gate turning on the device (the switch is closed) the MOSFET's Source and Drain terminals are shorted; otherwise, the switch is open.
Reducing MOSFET dimensions is a primary goal of device designers. Reducing the minimum device shade and size results in smaller, denser circuits and denser integrated circuit chips. Because device shapes are smaller, loads are smaller resulting in faster circuits and faster integrated circuit chips. Smaller, faster integrated circuit chips lead to smaller, faster, and more powerful systems, the ultimate goal.
An early attempt at reducing device sizes was V-groove technology (VMOS). V-groove MOSFETS had longer electrical channel lengths than physical length, i.e., the distance between the source and drain. The VMOS device's drain and source were on opposite sides of the groove with the channel in the groove. So, these VMOS devices provided a way to reduce physical dimensions without reducing electrical dimensions.
However, reducing MOSFET electrical dimensions resulted in problems known, generally, as short channel effects. One such problem, avalanche effect, is the result of a reduced pinchoff voltage V.sub.p for short channel devices. Avalanche effect leads to channel current leakage into the substrate. To reduce avalanche effect, the drain voltage for short channel MOSFETs is limited. For short channel devices, avalanche effect may be more troublesome than simply causing substrate leakage. Substrate leakage current may be sufficient to forward bias the source to substrate junction. This junction also behaves as the base-emitter junction of a parasitic lateral transistor with the device's drain acting as the collector. At sufficient substrate leakage, the parasitic transistor turns on, and amplifies the leakage so that the drain to source leakage is several times the normal channel leakage. With sufficient leakage, the device fails catastrophically.
One approach to reducing avalanche effect for short channel devices was to reduce the substrate doping level (to about 10.sup.15 cm.sup.-3). Reducing the doping level increases leakage resistance. However, low substrate doping extends the drain's depletion layer. For short channel devices, the drain's depletion layer extends into the source's depletion layer, causing punchthrough. Further, increasing drain voltage reduces the source junction barrier to increase punchthrough. Thus, prior art device designers were faced with the dilemma of either increasing the channel dopant level and accepting the risk of avalanche breakdown, or, of reducing the dopant level and risking incurring equally disastrous punchthrough problems. However, both alternatives required reducing operating voltages.
Additionally, there is always source minimum substrate leakage because, regardless of the magnitude of the drain to source voltage V.sub.ds, some electrons flow into the substrate. Electron flow is intended to be horizontal, through the channel from the source to the drain. Because the source and drain regions are ion implanted, the channel's doping profile peak is near the silicon surface and decreases exponentially, vertically, into the substrate. The electric field created by the doping profile forces electrons downward, not laterally as intended. This downward field is the cause of that minimum substrate leakage.